Focal plane array with modular pixel array components for scalability
| DWPI Title: Focal plane array apparatus such as integrated circuit apparatus for imaging system, has routing structure that is provided to couple array of pixels to signal processing circuitry and configured to extend through gap area |
| Abstract: A modular, scalable focal plane array is provided as an array of integrated circuit dice, wherein each die includes a given amount of modular pixel array circuitry. The array of dice effectively multiplies the amount of modular pixel array circuitry to produce a larger pixel array without increasing die size. Desired pixel pitch across the enlarged pixel array is preserved by forming die stacks with each pixel array circuitry die stacked on a separate die that contains the corresponding signal processing circuitry. Techniques for die stack interconnections and die stack placement are implemented to ensure that the desired pixel pitch is preserved across the enlarged pixel array. |
| Use: Focal plane array apparatus such as integrated circuit apparatus for imaging system (all claimed). |
| Advantage: Since the array of the dice is provided, the amount of modular pixel array circuitry is effectively multiplied to produce a larger pixel array and thus the die size is reduced. Since the face to face arrangement is provided, the front surfaces of the dice are protected, and the planarization of the back side of the pixel layer dice is facilitated. Since the electro-optical interface is utilized, the relatively large amounts of data is transferred at relatively high sampling rates, and thus better exploitation of the increased size of an focal plane array (FPA) is enabled. |
| Novelty: The apparatus has multiple die stacks (21) that are mounted on a substrate. An image detector is provided with array of pixels. A first die is provided with sub-array portions and a gap area that is configured to separate sub-array portions from one another. The die stacks are separated from one another on substrate. The sub-array portions are separated from a peripheral edge of first die by a distance that is less than first common pixel width in first die. A routing structure is provided to couple array of pixels to signal processing circuitry and extended through gap area. |
| Filed: 6/20/2011 |
| Application Number: US13163909A |
| Tech ID: SD 10909.1 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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