Via configuration for wafer-to-wafer interconnection
| DWPI Title: Vertically-stacked integrated circuit assembly for providing reliable and repeatable electrical bonding, has first and second integrated circuit substrates arranged such that one of bond posts overlaps portion of one of bond posts |
| Abstract: A modification to the standard layout of vias used for vertically-stacked wafer bonding is proposed which has been found to improve the interconnect overlay while avoiding the dishing problems associated with the planarization processes used in the creation of conductive posts within the vias. In particular, the pitch, i.e. the spacing between adjacent posts, is intentionally chosen to be different for each wafer. By using different pitches, there is an increase in the probability of overlap of posts on each wafer, even when one wafer is slightly offset with respect to the other (which is possible when aligning one wafer with another in a standard bonding tool). Advantageously, the use of different pitches allows for the use of relatively small diameter (one micron or less) posts while still creating sufficient overlap for the necessary connections. |
| Use: Vertically-stacked integrated circuit assembly for providing reliable and repeatable electrical bonding between wafers within the stack. |
| Advantage: The assembly has cost-effective three dimensional wafer configurations for providing reliable and repeatable electrical bonding between wafers within the stack. |
| Novelty: The assembly has a first integrated circuit substrate including a first set of bond posts with adjacent bond posts separated by a predetermined first pitch Pbot. A second integrated circuit substrate includes a second set of bond posts with adjacent bond posts of the second set of bond posts separated by a predetermined second pitch Ptop and each of the second set of bond posts exhibits a diameter D2 less than Ptop. The first integrated circuit substrate and the second integrated circuit substrate are arranged such that one of the bond posts overlaps a portion of one of the bond posts. The first integrated circuit substrate and the second integrated circuit substrate are connected between the overlapped portions of one of the bond posts. |
| Filed: 5/23/2017 |
| Application Number: US15603100A |
| Tech ID: SD 14069.0 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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