Ultra-low power processor-in-memory architecture

DWPI Title: General-purpose computing apparatus has switch electrically connects to particular row of rows of memory array per cycle, and energy storage unit electrically connected to memory array through switch allowing bi-directional flow of energy
Abstract: An apparatus including a memory array comprising a plurality of rows and a plurality of columns. A switch electrically connects to a particular row of the plurality of rows of the memory array per cycle. An energy storage unit is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.
Use: General-purpose computing apparatus.
Advantage: Improves the energy efficiency and reliability of computing systems. Enables error mitigation for systems using signals of lower signal power without completely.
Novelty: The general-purpose computing apparatus has a memory array having rows and columns, and a switch that electrically connects to a particular row of rows of the memory array per cycle. An energy storage unit is electrically connected to the memory array through the switch.
Filed: 11/28/2017
Application Number: US15824879A
Tech ID: SD 13081.2
This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention.
Data from Derwent World Patents Index, provided by Clarivate
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