| Abstract: | A 3D stacked sASIC is provided that includes a plurality of 2D
reconfigurable structured structured ASIC (sASIC) levels interconnected
through hard-wired arrays of 3D vias. The 2D sASIC levels may contain
logic, memory, analog functions, and device input/output pad circuitry.
During fabrication, these 2D sASIC levels are stacked on top of each
other and fused together with 3D metal vias. Such 3D vias may be
fabricated as through-silicon vias (TSVs). They may connect to the
back-side of the 2D sASIC level, or they may be connected to top metal
pads on the front-side of the 2D sASIC level. |