| Abstract: A 3D stacked sASIC is provided that includes a plurality of 2D
reconfigurable structured structured ASIC (sASIC) levels interconnected
through hard-wired arrays of 3D vias. The 2D sASIC levels may contain
logic, memory, analog functions, and device input/output pad circuitry.
During fabrication, these 2D sASIC levels are stacked on top of each
other and fused together with 3D metal vias. Such 3D vias may be
fabricated as through-silicon vias (TSVs). They may connect to the
back-side of the 2D sASIC level, or they may be connected to top metal
pads on the front-side of the 2D sASIC level. |
| Filed: 5/20/2014 |
| Application Number: 14/283101 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
| Attribution for Derwent World Patents Index Records published on Sandia ® Clarivate. All rights reserved. Republication or redistribution of Clarivate content, including by framing or similar means, is prohibited without the prior written consent of Clarivate. Clarivate and its logo, as well as all other trademarks used herein are trademarks of their respective owners and used under license. |