| Abstract: A method and apparatus for performing reliable general-purpose computing.
Each sub-core of a plurality of sub-cores of a processor core processes a
same instruction at a same time. A code analyzer receives a plurality of
residues that represents a code word corresponding to the same
instruction and an indication of whether the code word is a memory
address code or a data code from the plurality of sub-cores. The code
analyzer determines whether the plurality of residues are consistent or
inconsistent. The code analyzer and the plurality of sub-cores perform a
set of operations based on whether the code word is a memory address code
or a data code and a determination of whether the plurality of residues
are consistent or inconsistent. |
| Filed: 8/20/2015 |
| Application Number: 14/831711 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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