Multi-channel high-speed converter clock synchronization with autonomous coherent deterministic latency
| DWPI Title: Method for autonomously achieving coherency and deterministic latency (CDL) in multi-channel system e.g. radar system, involves resetting and disabling clock dividers, and enabling clock generation |
| Abstract: A system and corresponding method that achieves coherency and deterministic latency (CDL) autonomously upon power on is disclosed. The system, for example, a multi-channel RF system, may require CDL with respect to the digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) assigned to the channels in the system. CDL is achieved through a timed combination of external reference and synchronization signals, resetting and disabling of various clock dividers, and enabling clock generation. In addition to synchronizing all of the clocks, the data acquisition sequence must be synchronized across all of the channels, whether they are on chips, cards, or chassis. Data acquisition synchronization may be implemented using an initiator/target or a wired OR mode configuration. |
| Use: Method for autonomously achieving coherency and deterministic latency in a multi-channel system for radar and other radio frequency (RF) applications. |
| Advantage: The method enables achieving coherency and deterministic latency (CDL) through a timed combination of external reference and synchronization signals, resetting and disabling the various clock dividers, and enabling clock generation. The method synchronizes the data acquisition sequence across all of the channels, whether they are on chips, cards, or installed in a different chassis. The data acquisition synchronization can be implemented using an initiator/target or a wired OR mode configuration. |
| Novelty: The method involves sending and releasing a corresponding synchronization command issued by a corresponding controller to a corresponding system reference clock generator and a corresponding phase lock loop (PLL) to cause each synchronization/system reference signal, each local system clock signal, and the corresponding divided clock signals to be coherent with an external reference clock signal. The resetting of each local clock divider and corresponding one or more clock dividers is disabled via a corresponding command. The generation of each synchronization or system reference signal is enabled by the system reference generator via the command. Each converter master trigger signal is generated. The conversion is initiated by the corresponding one of a digital-to-analog converter (DAC) or an ADC. |
| Filed: 9/8/2021 |
| Application Number: US17469023A |
| Tech ID: SD 15168.0 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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