Method for modifying or verifying a circuit by inserting a saboteur circuit
| DWPI Title: Method for realizing circuit modification for fault mitigation in Field programmable gate array (FPGA) circuit, involves retaining redundant circuit in modified netlist if first net of netlist passes testing, and removing redundant circuit from modified netlist if first net does not pass testing |
| Abstract: A method for circuit modification for fault mitigation including: obtaining a netlist defining a circuit; inserting at least one saboteur circuit into a first net of the netlist; configuring an FPGA to implement the first net and the at least one saboteur circuit; activating a first of the at least one saboteur circuits; determining whether the first net experiences a fault; and upon determining that the first net experiences a fault, modifying the first net by inserting at least one redundant circuit into the first net. |
| Use: Method for realizing circuit modification for fault mitigation in FPGA circuit. |
| Advantage: The method enables realizing mitigations to ensure critical components continue to operate in presence of hardware faults, and allowing possibility of resilience against common mode failures in addition to transient upsets, and realizing introduction of redundant logic to portions of net observed to comprise severe fault to reduce overhead required by triple modular redundant implementations of complete circuit. |
| Novelty: The method involves obtaining (202) a netlist, where the netlist is formed with a circuit. A saboteur circuit is inserted (204) into a first net of the netlist. An FPGA is configured (206) to implement the first net and the saboteur circuit. A first saboteur circuit is activated (208). Determination is made (210) to check whether the first net experiences fault. The first net is modified by inserting a redundant circuit into the first net if the first net experiences fault. Modified netlist corresponding to the netlist and the redundant circuit are obtained. A second saboteur circuit is inserted into first net of the modified netlist. The FPGA is configured to implement the first net of the modified netlist and the second saboteur circuit. The second saboteur circuit is activated. The first net of the modified netlist is tested. |
| Filed: 4/25/2023 |
| Application Number: US18139148A |
| Tech ID: SD 16397.0 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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