Field programmable gate array bitstream verification

Patent Number: 10,262,098
Issued: 4/16/2019
Official Filing: View the Complete Patent
Abstract: Described herein are various technologies pertaining to confirming an integrity of a FPGA. A verifier circuit is placed into an FPGA bitstream to enable external verification of the FPGA configuration in real time without requiring readout of the FPGA configuration itself. Number generators are utilized to generate a key which is shared between the FPGA and an external verification component (VC). The key is utilized to configure an initial state of sequence registers respectively located on both the FPGA and the VC. When the FPGA is operating with an approved configuration, output from the sequence registers at the FPGA and the VC are the same.
Filed: 10/29/2015
Application Number: 14/927,046
Government Interests: STATEMENT OF GOVERNMENT INTEREST This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention.