Complementary current reuse even harmonic frequency multiplier
| DWPI Title: Complementary current reuse frequency doubler device for use in millimeter wave radio frequency applications, has P-type metal oxide semiconductor transistors and negative-channel metal oxide semiconductor transistors whose sizes are adapted to provide equivalent transconductances |
| Abstract: An even harmonic multiplier employing complementary current reuse is disclosed. The even harmonic multiplier employs supply voltage and current density scaling to reduce power consumption. Further, by using complimentary NMOS and PMOS transistors, the even harmonic multiplier achieves high areal efficiency. Current reuse causes a reduction in noise at the first harmonic, as the corresponding first harmonic currents from the NMOS and PMOS transistors are in opposite, i.e., canceling, directions. Complementary current reuse is now feasible, as the performance of PMOS transistors at current process nodes is similar to those of NMOS transistors, with appropriate sizing leading to approximately equivalent transconductances. Multiple even harmonic multiplier configurations are possible, with many using transformer circuits at the input and/or the output. The resultant even harmonic multipliers find ready application in millimeter wave radio frequency receivers. The most common even harmonic multiplier is a frequency doubler, which produces a strong second harmonic signal. |
| Use: CCR frequency doubler device for use in millimeter wave radio frequency applications. |
| Advantage: The device combines low power consumption due to the supply voltage and current density scaling, with high areal efficiency, making them ideal for millimeter wave radio frequency applications. The device causes a drastic reduction in noise at the first harmonic as the corresponding first harmonic currents from the NMOS and PMOS transistors are in opposite directions. |
| Novelty: The device (2800) has a complementary current reuse (CCR) even harmonic multiplier including positive-channel metal oxide semiconductor (PMOS) transistors (2810A, 2810B), where drains of the PMOS transistors are coupled together at a first output node. Negative-channel metal oxide semiconductor (NMOS) transistors (2820A, 2820B) are coupled at a second output node. The first and second output nodes (2840) are adapted to output an output signal at a frequency, where sizes of the first and second PMOS transistors and the first and second NMOS transistors are adapted to provide equivalent transconductances. |
| Filed: 1/18/2024 |
| Application Number: US18415778A |
| Tech ID: SD 16387.1 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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