Area-efficient physically unclonable function circuit architecture
| DWPI Title: Method for generating physically unclonable function circuit value, involves generating output voltage representative of difference between two capacitors, where output voltage is compared to reference voltage during generating bit value |
| Abstract: Generating a physically a physically unclonable function (“PUF”) circuit value includes comparing each of first identification components in a first bank to each of second identification components in a second bank. A given first identification component in the first bank is not compared to another first identification component in the first bank and a given second identification component in the second bank is not compared to another second identification component in the second bank. A digital bit value is generated for each comparison made while comparing each of the first identification components to each of the second identification components. A PUF circuit value is generated from the digital bit values from each comparison made. |
| Use: Method for generating a PUF circuit value. |
| Advantage: The method enables comparing the capacitors by counting the counts of an integrating oscillator when a given capacitor is coupled to the integrating oscillator and performing process of tracing the origin of the hardware component to form a deterrent against insertion of a subversion or substitution of a subverted component by an adversary to avoid attribution upon subsequent discovery of the subversion so as to avoid providing attribution of subversions introduced during deployed life of the device and permit detection of tampering. |
| Novelty: The method involves generating a digital bit value for different comparisons made while comparing a first set of identification components to a second set of identification components. A physically unclonable function (PUF) circuit value is generated from the digital bit values generated from the comparisons made. Charge on two capacitors (125, 130) is unbalanced and rebalanced after unbalancing the charge. Output voltage representative of difference between the capacitors is generated, where the output voltage is compared to reference voltage during generating the digital bit value. |
| Filed: 5/31/2013 |
| Application Number: US13906628A |
| Tech ID: SD 12330.2 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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