Architectural support for persistent applications
| DWPI Title: Method for architectural support of hybrid memory system persistent applications, involves caching fraction of data stored in non-volatile memory in mirror region of dynamic random access memory |
| Abstract: Illustrative embodiments are directed to methods, apparatus and computer program products for caching at least a fraction of data stored in a non-volatile memory in a mirror region of a dynamic random access memory. A memory controller hub of a processor chip coupled to both the non-volatile memory and the dynamic random access memory is configured to, when an update to the dynamic random access memory is cached in the mirror region of the dynamic random access memory, use the memory controller hub to write the update directly to the mirror region of the dynamic random access memory and concurrently mirror the update to the non-volatile memory to provide coherent persistent durability of the update. When a read from the dynamic random access memory is cached in the mirror region of the dynamic random access memory, embodiments can use the memory controller hub to serve the read directly from the mirror region of the dynamic random access memory to optimize read operations of persistent objects. |
| Use: Method for architectural support of hybrid memory system persistent applications. |
| Advantage: The method involves caching a fraction of data stored in a non-volatile memory in a mirror region of a dynamic random access memory, where a memory controller hub of a processor chip is coupled to both the non- volatile memory and the dynamic RAM, and hence ensures simple and efficient architectural support of hybrid memory system persistent applications. |
| Novelty: The method involves caching a fraction of data stored in a non-volatile memory in a mirror region of a dynamic random access memory (DRAM) (640). A memory controller hub of a processor chip is coupled to both the non- volatile memory and the DRAM. The update is written directly to the mirror region and the update is concurrently mirrored to the non volatile memory to provide coherent persistent durability of the update, when an update to the dynamic RAM is cached in mirror region. The read operation of persistent objects is optimized, when a read from the dynamic DRAM is cached. |
| Filed: 2/4/2022 |
| Application Number: US17665390A |
| Tech ID: SD 15660.0 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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