Single clock delay step in multi-stage switched-capacitor delays
| DWPI Title: Programmable delay device for use in multi-stage switched capacitors of complementary MOS circuitry on single silicon substrate used in different applications, has reconstruction stage for outputting reconstruction signals in sequential manner for generating reconstructed radio frequency signal |
| Abstract: A programmable delay device providing a delay resolution of less than 1 ns and a maximum delay of >100 ns over a broad bandwidth is disclosed. The device includes an input stage with M sampling switched capacitor elements, reducing the sampling rate by M. The device includes a programmable delay stage with M programmable switched capacitor banks, each bank having N delay switched capacitor storage elements. The programmable delay stage includes a total of M×N delay switched capacitor storage elements, reducing the sampling rate by M×N. This reduced sampling rate permits smaller sampling switches, with reduced leakage current and longer programmable delay times. The device includes an output reconstruction stage that reconstructs a delayed version of the input signal by combining signals from the programmable delay stage. The sampling clocks for the input and output reconstruction stages are independent, allowing a delay resolution corresponding to the sampling rate. |
| Use: Programmable delay device for use in multi-stage switched capacitors of a complementary MOS (CMOS) circuitry on a single silicon substrate used in different applications. Uses include but are not limited to radar testers, analog correlators, finite impulse response (FIR) filters, digital radio frequency (RF) memories, broadband phased array applications and large radar and communication systems. |
| Advantage: The reduced sampling rate permits the use of much smaller sampling switches, resulting in reduced leakage current and the ability to implement far longer programmable delay times. The device provides a minimum delay resolution of less than 1 ns, while maintaining a maximum delay of more than 100 ns over a broad bandwidth. The delay buffers are deleted leading to a passive implementation, thus creating a tradeoff between power consumption, loss of gain, area, and area efficiency. The device allows the use of smaller input switched bank switches in the delay switched capacitor storage elements of a programmable delay stage, which enables large reduction in OFF state sample leakage. The sampler bandwidth required in the programmable delay stage is greatly reduced with the expanded sample time. The inductorless low noise amplifier (LNA) receives an input RF signal and provides gain and differential conversion with NMOS bias sharing to reduce AC coupling capacitors for area savings. The sampling switched capacitor storage element employs a differential capacitor having capacitance of 250 fF for small area and sampling noise. The relatively long length devices are preferably employed for intervening buffers to reduce direct current (DC) offset. |
| Novelty: The device (300) has an enable timing circuit (352) including a digital counter. The digital counter is adapted to count to a desired coarse delay value. The enable timing circuit is adapted to output an output reconstruction clock and an incremental coarse delay value corresponding to M/FS upon reaching the desired coarse delay value. An output reconstruction stage (318) includes output reconstruction switches. Each output reconstruction switch is coupled to a delay output switch. Each output reconstruction switch is adapted to output a time interleaved delay sampled switched signal based on the output reconstruction clock, the time interleaved delay sampled switched signal output reconstruction signals. The output reconstruction stage is adapted to output the output reconstruction signals in a sequential manner for generating a reconstructed output radio frequency (RF) signal. |
| Filed: 3/26/2024 |
| Application Number: US18616962A |
| Tech ID: SD 16371.0 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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