Large programmable delay at high frequency through aliasing
| DWPI Title: Programmable alias delay device for manipulating radio frequency signals by employing time-interleaved multistage switched-capacitor architecture, has output reconstruction switch coupled to corresponding delay output switch |
| Abstract: A programmable alias delay device providing output in a desired frequency band and a maximum delay of >5 ns over a broad bandwidth and at a high frequency is disclosed. The device includes an input bandpass filter and an input stage with M sampling switched capacitor elements, reducing the sampling rate by M. The device includes a programmable delay stage with M programmable switched capacitor banks, each bank having N delay switched capacitor storage elements, reducing the sampling rate by M×N. This reduced sampling rate permits smaller sampling switches, with reduced leakage current and longer programmable delay times. The device includes an output reconstruction stage that reconstructs a delayed version of the input signal by combining signals from the programmable delay stage. Using a subsequent output alias filter, an alias band in the desired frequency band is selected and output. |
| Use: Programmable alias delay device for manipulating radio frequency (RF) signals by employing time-interleaved multistage switched-capacitor (TIMS-SC) architecture. |
| Advantage: The programmable alias delay device for providing output in a desired frequency band and a maximum delay of greater than 5 ns over a broad bandwidth and at a high frequency. The device includes a programmable delay stage with M programmable switched capacitor banks, each bank having N delay switched capacitor storage elements, reducing the sampling rate by M×N and reduced sampling rate permits smaller sampling switches, with reduced leakage current and longer programmable delay times. The multi-stage switched capacitors achieve a large programmable delay using aliasing and achieves through series of stages to achieve desired delay effect. The sampler bandwidth required in the programmable delay stage is greatly reduced and allows the use of much smaller input switched bank switches in the delay switched capacitor storage elements of the programmable delay stage, which in turn enables a large reduction in OFF state sample leakage. The reduced sampling rate permits the use of much smaller sampling switches, resulting in reduced leakage current and the ability to implement far longer programmable delay times. |
| Novelty: The device has an output reconstruction stage including M output reconstruction switches, where each output reconstruction switch is coupled to a corresponding delay output switch. Each output reconstruction switch is adapted to output a corresponding time interleaved delay sampled switched signal based upon the output reconstruction clock, thus output time interleaved delay sampled switched signals is being output reconstruction signals, the output reconstruction stage is adapted to output the output reconstruction signals in a sequential manner thus generating a reconstructed delayed output RF signal. An output alias filter is adapted to receive the reconstructed delayed output RF signal and to filter the reconstructed delayed output RF signal, thus generating an alias band output RF signal in a desired output frequency band. |
| Filed: 7/17/2024 |
| Application Number: US18775675A |
| Tech ID: SD 16104.0 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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