Integrated circuit test-port architecture and method and apparatus of test-port generation
| DWPI Title: Design method for Design for Test (DFT) integrated circuits, involves recording representation in register transfer level (RTL) code which logically defines all wires and required ports |
| Abstract: A method and apparatus are provided for generating RTL code for a test-port interface of an integrated circuit. In an embodiment, a test-port table is provided as input data. A computer automatically parses the test-port table into data structures and analyzes it to determine input, output, local, and output-enable port names. The computer generates address-detect and test-enable logic constructed from combinational functions. The computer generates one-hot multiplexer logic for at least some of the output ports. The one-hot multiplexer logic for each port is generated so as to enable the port to toggle between data signals and test signals. The computer then completes the generation of the RTL code. |
| Use: Design method for Design for Test (DFT) integrated circuits. |
| Advantage: The new test-port architecture has special features that facilitate the automated code generation. The Automatic Test Pattern Generation (ATPG) Test Mode enables the internal logic scan chains and allows the design to be tested with ATPG vectors. |
| Novelty: The method involves providing a configuration that relates defined signals to corresponding test-port pins of a test-port interface. The pin requirements are automatically analyzed for the test-port interface. The multiplexer logic configured to allow only a single input at each given time, such that each port can toggle between data signals and test signals is generated. A representation in RTL code of a test-port interface which logically defines all wires and ports required to implement the configurations specified in the specification table is recorded. |
| Filed: 7/10/2014 |
| Application Number: US14328379A |
| Tech ID: SD 12906.0 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
| Data from Derwent World Patents Index, provided by Clarivate All rights reserved. Republication or redistribution of Clarivate content, including by framing or similar means, is prohibited without the prior written consent of Clarivate. Clarivate and its logo, as well as all other trademarks used herein are trademarks of their respective owners and used under license. |