Silicon nanowire device and method for its manufacture

DWPI Title: Electronic device has metal contact pad which is connected to top gate polysilicon layer through interconnect that passes through interlayer dielectric region, in which top gate polysilicon layer is connected to polysilicon gate conductor
Abstract: There is provided an electronic device and a method for its manufacture. The device comprises an elongate silicon nanowire less than 0.5 μm in cross-sectional dimensions and having a hexagonal cross-sectional shape due to annealing-induced energy relaxation.
Use: Electronic device.
Advantage: The nanowires is placed in precisely specified locations and standard CMOS doped regions is defined for source and drain contacts since initial device position is defined by lithography. Modifies wire cross-sectional dimension and shape by high temperature annealing to generate a hexagonal, energy minimized configuration.
Novelty: The device has a metal contact pad which is electrically connected to a top gate polysilicon layer through an interconnect that passes vertically through an interlayer dielectric region, in which the top gate polysilicon layer is electrically connected to the polysilicon gate conductor. The elongate silicon nanowire is conformed with selectively thinned portions that define electrically isolated nodules of silicon, and is included in a complementary metal-oxide-semiconductor integrated circuit. The elongate silicon nanowire is less than 50 nanometers in cross sectional dimensions.
Filed: 8/14/2013
Application Number: US13966553A
Tech ID: SD 12077.0
This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention.
Data from Derwent World Patents Index, provided by Clarivate
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