Processor-in-memory-and-storage architecture
| DWPI Title: Apparatus for performing reliable general-purpose computing operation in computing system, has code analyzer being in communication with memory and performing error mitigation using code words received from sub-cores of processor core |
| Abstract: A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent. |
| Use: Apparatus for performing reliable general-purpose computing operation in a computing system (claimed). |
| Advantage: The apparatus increases recycled energy to improve overall energy efficiency of the computing system within which an adiabatic memory circuit is used by using sophisticated circuit components and error correction codes without sacrificing performance. |
| Novelty: The apparatus has a processor core (114) being in communication with a memory. The processor core comprises sub-cores (118) in which a numeric range of each of the sub-cores is less than a total numeric range (116) of the processor core. A code analyzer (124) is in communication with the memory and the sub-cores of the processor core, and performs error mitigation using code words (125) received from the sub-cores. The code analyzer performs data error detection using residues received from the sub-cores in which the residues represent the code word. |
| Filed: 8/20/2015 |
| Application Number: US14831711A |
| Tech ID: SD 13081.0 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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