Integrated circuit physically unclonable function
| DWPI Title: Apparatus for integrated circuit (IC) physically unclonable function (PUF), has gate terminal of metal oxide semiconductor (MOS) transistors are connected through switching arrangement to common gate terminal of output stage transistor unit |
| Abstract: An integrated circuit (IC) based physically unclonable function (PUF) that comprises a common source amplifier for generating PUF output voltages, a unity gain, negative feedback operational amplifier for generating bias voltages, a voltage regulator and a bit exclusion circuit that excludes unstable PUF bits. Compensation circuitry built into the IC-PUF provides a high power supply rejection ratio and enables highly reliable operation of the IC-PUF across varying input voltages and operating temperatures. The IC-PUF generates a uniformly random output bit stream by taking advantage of process variations that are inherent to the fabrication of (metal-oxide semiconductor) MOS transistors. |
| Use: Apparatus for integrated circuit (IC) based physically unclonable function (PUF) is used in application such as anti-counterfeiting of electronic and cryptography. |
| Advantage: The error mitigation approach minimizes that are otherwise required to ensure error-free operation over the life of a PUF. The major improvement that the IC-PUF provides over the state of the art in PUF technology is superior reliability achieved through compensation circuitry built into the IC-PUF circuit that provides a high power supply rejection ratio and small IC-PUF output variations across varying operating power supply voltage, temperature and aging. The reliability of the PUF generator is improved significantly by mitigating power supply variations through the use of the voltage regulator and the operational amplifier. The PUF mask is used by the bit-exclusion circuit in order to exclude the unstable bits, generated by the unstable PUF elements from the final bit stream to ensure highly reliable and error-free operation of the IC-PUF. This enables very robust PUF output without for undesirable error-correcting code and undesirable helper data. |
| Novelty: The apparatus has a negative input terminal of a first stage is connected between a NMOS common drain terminal and a PMOS common drain terminal of an output stage. A respective PUF common source amplifier comprises a first MOS transistor and a second MOS transistor. A first bias voltage is input to a switch that applies it as a switched first bias voltage to a gate terminal of the first MOS transistor. The second bias voltage is input to a switch that applies it as a switched second bias voltage to the gate terminal of the second MOS transistor. The gate terminal of the first MOS transistor is connected through an applicable switching arrangement to the common gate terminal of one of the output stage transistor units. The gate terminal of the second MOS transistor is connected through the applicable switching arrangement to a common gate terminal of the other output stage transistor unit. |
| Filed: 11/20/2017 |
| Application Number: US15817870A |
| Tech ID: SD 14078.1 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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