Hybrid CMOS-MEMS devices adapted for high-temperature operation and method for their manufacture

DWPI Title: Apparatus for manufacturing microelectromechanical systems (MEMS), has cavity that is bounded from above by material of structural layer and bounded from below by material of post-MOS passivation layer respectively
Abstract: A silicon carbide based MOS integrated circuit is monolithically integrated with a suspended piezoelectric aluminum nitride member to form a high-temperature-capable hybrid MEMS-over-MOS structure. In the integrated structure, a post-MOS passivation layer of silicon carbide is deposited over the MOS passivation and overlain by a structural layer of the MEMS device. Electrical contact to refractory metal conductors of the MOS integrated circuit is provided by tungsten vias that are formed so as to pass vertically through the structural layer and the post-MOS passivation layer.
Use: Apparatus for manufacturing microelectromechanical systems used in high-temperature metal oxide semiconductor (MOS) integrated circuit.
Advantage: The electrical contact to refractory metal conductors of the MOS integrated circuit is provided by tungsten are formed, so as to pass vertically through the structural layer and the post-MOS passivation layer.
Novelty: The apparatus has a high-temperature-capable metal oxide semiconductor (MOS) component that is monolithically integrated with a post-MOS component with a suspended piezoelectric aluminum nitride portion. The MOS component has MOS integrated circuit which is formed in a high-temperature-capable substrate. The MOS integrated circuit has multiple levels of refractory metal conductors isolated by an MOS passivation layer of dielectric material. The vertical conductor has the same composition as portion of the top electrode. One bottom-electrode is set through the structural layer and through the post-MOS passivation layer. The bottom-electrode via connects the bottom electrode to a refractory metal conductor of the MOS integrated circuit. The cavity is bounded from above by material of the structural layer and bounded from below by material of the post-MOS passivation layer.
Filed: 3/2/2018
Application Number: US15910531A
Tech ID: SD 14088.0
This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention.
Data from Derwent World Patents Index, provided by Clarivate
All rights reserved. Republication or redistribution of Clarivate content, including by framing or similar means, is prohibited without the prior written consent of Clarivate. Clarivate and its logo, as well as all other trademarks used herein are trademarks of their respective owners and used under license.