Field programmable gate array bitstream verification
| DWPI Title: System for detecting modification of field programmable gate array (FPGA), has verification component and FPGA that synchronously update states of first and second sequence generator based upon clock signals emitted from shared clock |
| Abstract: Described herein are various technologies pertaining to confirming an integrity of a FPGA. A verifier circuit is placed into an FPGA bitstream to enable external verification of the FPGA configuration in real time without requiring readout of the FPGA configuration itself. Number generators are utilized to generate a key which is shared between the FPGA and an external verification component (VC). The key is utilized to configure an initial state of sequence registers respectively located on both the FPGA and the VC. When the FPGA is operating with an approved configuration, output from the sequence registers at the FPGA and the VC are the same. |
| Use: System for detecting modification of field programmable gate array (FPGA) (claimed) to confirm integrity of FPGA. |
| Advantage: The verification can be performed in real-time without requiring readout of the FPGA configuration from memory of the FPGA. The correctness of a portion of the FPGA's configuration is checked, thus, the verification component can check the integrity of the entire configuration of the FPGA without interrupting operation of the FPGA. |
| Novelty: The system (200) has a FPGA (110) that comprises a first sequence generator having a first state. A verification component (120) is in communication with the FPGA. The verification component comprises a second sequence generator having a second state. The verification component verifies that the configuration is an approved configuration of the FPGA based upon the second state and data received from the FPGA. The verification component and the FPGA synchronously update states of the first and second sequence generator based upon clock signals emitted from a shared clock (160). The verification component determines that the configuration has been altered when a comparator component (275) determines that the current configuration setting is inequivalent to the test configuration setting. The operation of the FPGA is terminated responsive to the verification component determining that the configuration has been altered. |
| Filed: 10/29/2015 |
| Application Number: US14927046A |
| Tech ID: SD 11864.0 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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