FPGA/ASIC framework and method for requirements-based trust assessment

DWPI Title: System for detecting potential vulnerability in net-list of e.g. field-programmable gate arrays, has processor for outputting indication to user that node is labeled as indicative of potential vulnerability in net-list of logic devices
Abstract: Described herein are various technologies for metrics-based assessment and trust verification of netlists for hardware logic devices (e.g., ASICs, FPGAs, etc.). A computing system translates a netlist of a hardware logic device into a Boolean network. The computing system generates and assigns metrics to edges of the Boolean network. The metrics comprise a coverage metric, a rare trigger metric, and an influence metric. Based upon the metrics, the computing system assigns the nodes in the Boolean network criticality values. The computing system determines a likelihood of a vulnerability in the netlist based upon the criticality values. The computing can output an indication as to whether the netlist is trusted based upon the determined likelihood of a vulnerability in the netlist.
Use: System for detecting potential vulnerability in a net-list of hardware logic devices e.g. field-programmable gate arrays (FPGA) and application-specific integrated circuits (ASIC) (all claimed). Can also be used for application-specific standard products (AS SPs), system-on-a-chip systems (SOCs) and complex programmable logic devices (CPLDs).
Advantage: The system can detect potential vulnerability in the net-list of hardware logic devices in a rapid and accurate manner by outputting the indication to the user that the node is labeled as indicative of the potential vulnerability in the net-list.
Novelty: The system (100) has a processor (114) for determining influence of a node in a Boolean network based upon Fourier decomposition of a Boolean transfer function associated with the node, where an assessment metric is assigned based upon the determination. The processor labels the node in the Boolean network as an indicative of potential vulnerability in a net-list based upon the assessment metric, where the label indicates that the node corresponds to logic in the net-list that is susceptible to the vulnerability. The processor outputs an indication to a user that the node is labeled as an indicative of the potential vulnerability in the net-list.
Filed: 3/1/2017
Application Number: US15446787A
Tech ID: SD 13630.0
This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention.
Data from Derwent World Patents Index, provided by Clarivate
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