Analog vector-matrix multiplication by capacitive elements with resistive state storage
| DWPI Title: System for computation of vector-matrix multiplication (VMM), has integrator circuit whose output is based upon charging of capacitor and is indicative of matrix multiplication result |
| Abstract: An array circuit includes a plurality of vector-matrix multiplication (VMM) elements arranged in rows and columns. The VMM elements are configured to collectively perform multiplication of an input vector by a programmed input matrix to generate a plurality of output values that are representative of a result matrix that is the result of multiplication of the input vector and the input matrix. The VMM elements store states of the input matrix. Input voltages to the array are representative of elements of the input vector. A VMM element draws charge from a column read line based upon charging of a capacitor in the VMM. An integrator circuit connected to the column read line outputs a voltage that is indicative of a total charge drawn from the column read line by elements connected to the read line, which voltage is further indicative of an element of a result matrix. |
| Use: System for performing array circuit for computation of vector-matrix multiplication (VMM) used in various areas of computing technology, including artificial neural networks. |
| Advantage: The array circuit comprises multiple rows and multiple columns, where array circuit is referenced by row-column pairs, and thus enables to reduce the power consumption of the array circuit and improves the performance and utility of the devices. |
| Novelty: The system has a vector-matrix multiplication (VMM) element (114) provided with a capacitor connected to a first node and a second node. A non-volatile memory (NVM) element is connected to the first node and a third node. An electrical characteristic of the NVM element is indicative of a value of an element of an input matrix. An integrator circuit (116) is connected to the second node. The capacitor charges are provided in which responsive to a voltage is applied to the third node. An output of the integrator circuit is based upon the charging of the capacitor. The output of the integrator circuit is indicative of a matrix multiplication result. |
| Filed: 9/24/2020 |
| Application Number: US17031001A |
| Tech ID: SD 15180.0 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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