Vertical tunneling field-effect transistor with enhanced current confinement
| DWPI Title: Apparatus, preferably vertical tunneling field-effect transistor, comprises gate dielectric overlays the epitaxial cap layer for forming gate dielectric interface between epitaxial cap layer and gate dielectric, and gate overlays gate dielectric, where gate is adapted to receive operating bias |
| Abstract: A vertical tunneling field-effect transistor and a method for its manufacture are provided. According to methods herein disclosed, oppositely doped source and drain regions are formed, and an APAM delta layer is formed in the surface of the transistor substrate, beneath a metal gate, in electrical contact with, e.g., the source region. A dielectric layer intervenes between the substrate surface and the metal gate. An epitaxial cap layer directly over the APAM layer forms a dielectric layer interface with a dielectric layer, which is located between the epitaxial cap layer and the metal gate. A vertical channel is defined for tunneling between the APAM delta layer and an induced conduction channel adjacent to the dielectric layer interface that is formed in operation, and that is in electrical contact with, e.g., the drain region. |
| Use: Apparatus, preferably vertical tunneling field-effect transistor. |
| Advantage: The tunneling field effect transistor allows current to scale with the area of the device, and not merely with the junction width, so that higher current limits can be attained, achieves two-dimensional confinement, and allows the tunneling current to scale with the junction area, thus boosting the current limit of the device. |
| Novelty: Apparatus comprises a substrate having a surface, a first region doped to have a first type in a first portion of the substrate, a second region doped to have a second type opposite the first type. The second region in a second portion of the substrate different from the first portion. An atomic precision advanced manufacturing (APAM) delta layer (130) is formed in electrical contact with one of the first region or the second region. An epitaxial cap layer is formed directly on the APAM delta layer. A gate dielectric (140) overlays the epitaxial cap layer for forming a gate dielectric interface between the epitaxial cap layer and the gate dielectric. A gate overlays the gate dielectric, where the gate is adapted to receive an operating bias. |
| Filed: 6/2/2022 |
| Application Number: US17830874A |
| Tech ID: SD 15709.1 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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