Method to fabricate multi-level silicon-based microstructures via use of an etching delay layer

Patent Number: 6,930,051
Issued: 8/16/2005
Official Filing: View the Complete Patent
Abstract: New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Structures having features with different depth can be formed thereby in a single etching step.
Filed: 6/6/2002
Application Number: 10/165,861
Government Interests: STATEMENT OF GOVERNMENT INTEREST This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention.