Method to control artifacts of microstructural fabrication

Patent Number: 7,105,098
Issued: 9/12/2006
Official Filing: View the Complete Patent
Abstract: New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Compensation for etching-related structural artifacts can be accomplished by proper use of such an etching delay layer.
Filed: 6/6/2002
Application Number: 10/165,356
Government Interests: STATEMENT OF GOVERNMENT INTEREST This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention.