| Abstract: An apparatus and method are presented for identifying and mapping functional failures in an integrated circuit (IC) due to timing errors therein based on the generation of functional failures in the IC. This is done by providing a set of input test vectors to the IC and adjusting one or more: of the IC voltage, temperature or clock frequency; the rate at which the test vectors are provided to the IC; or the power level of a focused laser beam used to probe the IC and produce localized heating which changes the incidence of the functional failures in the IC which can be sensed for locating the IC circuit elements responsible for the functional failures. The present invention has applications for optimizing the design and fabrication of ICs, for failure analysis, and for qualification or validation testing of ICs. |
| Filed: 6/2/2000 |
| Application Number: 9/586505 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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