| Abstract: An NPN double heterostructure bipolar transistor (DHBT) is disclosed with a base region comprising a layer of p-type-doped indium gallium arsenide nitride (InGaAsN) sandwiched between n-type-doped collector and emitter regions. The use of InGaAsN for the base region lowers the transistor turn-on voltage, V.sub.on, thereby reducing power dissipation within the device. The NPN transistor, which has applications for forming low-power electronic circuitry, is formed on a gallium arsenide (GaAs) substrate and can be fabricated at commercial GaAs foundries. Methods for fabricating the NPN transistor are also disclosed. |
| Filed: 4/11/2000 |
| Application Number: 9/547152 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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