| Abstract: | Described herein are various technologies pertaining to confirming an
integrity of a FPGA. A verifier circuit is placed into an FPGA bitstream
to enable external verification of the FPGA configuration in real time
without requiring readout of the FPGA configuration itself. Number
generators are utilized to generate a key which is shared between the
FPGA and an external verification component (VC). The key is utilized to
configure an initial state of sequence registers respectively located on
both the FPGA and the VC. When the FPGA is operating with an approved
configuration, output from the sequence registers at the FPGA and the VC
are the same. |