| Abstract: A modification to the standard layout of vias used for vertically-stacked
wafer bonding is proposed which has been found to improve the
interconnect overlay while avoiding the dishing problems associated with
the planarization processes used in the creation of conductive posts
within the vias. In particular, the pitch, i.e. the spacing between
adjacent posts, is intentionally chosen to be different for each wafer.
By using different pitches, there is an increase in the probability of
overlap of posts on each wafer, even when one wafer is slightly offset
with respect to the other (which is possible when aligning one wafer with
another in a standard bonding tool). Advantageously, the use of different
pitches allows for the use of relatively small diameter (one micron or
less) posts while still creating sufficient overlap for the necessary
connections. |
| Filed: 5/23/2017 |
| Application Number: 15/603100 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
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