Algorithmic architecture co-design and exploration

Patent Number: 12105612
Issued: 10/1/2024
Official Filing: View the Complete Patent
Abstract: A method for matching neural network layouts to hardware architectures is provided. The method comprises iteratively: holding neural network parameters constant while changing a hardware architecture parameters, calculating a first loss value for a combination of the neural network parameters and hardware architecture parameters according to a gradient-based differentiable function within specified resource constraints, holding the hardware architecture parameters constant while changing the neural network parameters, calculating a second loss value for a new combination of parameters within the specified resource constraints, and combining the first loss value and the second loss value to calculate a combined loss value. The above iterative steps are stopped when the combined loss value reaches a specified threshold, and an optimal combination of neural network parameters and hardware architecture parameters is determined according to the combined loss value.
Filed: 8/30/2021
Government Interests: STATEMENT OF GOVERNMENT INTEREST This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention.