| Abstract: A method and apparatus are provided for generating RTL code for a
test-port interface of an integrated circuit. In an embodiment, a
test-port table is provided as input data. A computer automatically
parses the test-port table into data structures and analyzes it to
determine input, output, local, and output-enable port names. The
computer generates address-detect and test-enable logic constructed from
combinational functions. The computer generates one-hot multiplexer logic
for at least some of the output ports. The one-hot multiplexer logic for
each port is generated so as to enable the port to toggle between data
signals and test signals. The computer then completes the generation of
the RTL code. |
| Filed: 7/10/2014 |
| Application Number: 14/328379 |
| This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The Government has certain rights in the invention. |
| Attribution for Derwent World Patents Index Records published on Sandia ® Clarivate. All rights reserved. Republication or redistribution of Clarivate content, including by framing or similar means, is prohibited without the prior written consent of Clarivate. Clarivate and its logo, as well as all other trademarks used herein are trademarks of their respective owners and used under license. |