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Circuit arrangement and technique for setting matrix values in three-terminal memory cells
United States Patent
| 10,489,483 | |
| November 26, 2019 | |
| View the Complete Patent at the US Patent & Trademark Office | |
| A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change. | |
| 16/137,758 | |
| September 21, 2018 | |
| 1/1; | |
| G11C 11/34 (20060101); G06F 17/16 (20060101); G11C 16/04 (20060101); G06N 3/04 (20060101); H01L 29/792 (20060101); | |
| ;365/185.18 | |
| GOVERNMENT RIGHTS IN THE INVENTION This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The U.S. Government has certain rights in the invention. |