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FPGA/ASIC framework and method for requirements-based trust assessment

United States Patent

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September 10, 2019
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Described herein are various technologies for metrics-based assessment and trust verification of netlists for hardware logic devices (e.g., ASICs, FPGAs, etc.). A computing system translates a netlist of a hardware logic device into a Boolean network. The computing system generates and assigns metrics to edges of the Boolean network. The metrics comprise a coverage metric, a rare trigger metric, and an influence metric. Based upon the metrics, the computing system assigns the nodes in the Boolean network criticality values. The computing system determines a likelihood of a vulnerability in the netlist based upon the criticality values. The computing can output an indication as to whether the netlist is trusted based upon the determined likelihood of a vulnerability in the netlist.
March 1, 2017
G06F 11/00 (20060101); G06F 12/14 (20060101); G06F 12/16 (20060101); G08B 23/00 (20060101); G06F 21/76 (20130101); G06F 17/50 (20060101); G06F 21/57 (20130101);
STATEMENT OF GOVERNMENTAL INTEREST This invention was developed under Contract DE-AC04-94AL85000 between Sandia Corporation and the U.S. Department of Energy. The U.S. Government has certain rights in this invention.