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Ultra-low power processor-in-memory architecture

United States Patent

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10,083,080
September 25, 2018
View the Complete Patent at the US Patent & Trademark Office
An apparatus including a memory array comprising a plurality of rows and a plurality of columns. A switch electrically connects to a particular row of the plurality of rows of the memory array per cycle. An energy storage unit is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.
15/824,879
November 28, 2017
1/1;
G06F 11/00 (20060101); H03M 13/00 (20060101); G08C 25/00 (20060101); G06F 11/10 (20060101); G06F 1/32 (20060101);
GOVERNMENT LICENSE RIGHTS This invention was made with United States Government support under Contract No. DE-AC04-94AL85000 between Sandia Corporation and the United States Department of Energy and Contract No. DE-NA0003525 between National Technology & Engineering Solutions of Sandia, LLC and the United States Department of Energy/National Nuclear Security Administration. The United States Government has certain rights in this invention.