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Processor-in-memory-and-storage architecture

United States Patent

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9,858,144
January 2, 2018
View the Complete Patent at the US Patent & Trademark Office
A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.
14/831,711
August 20, 2015
1/1;
G11C 29/00 (20060101); G06F 11/10 (20060101);
GOVERNMENT LICENSE RIGHTS This invention was made with United States Government support under Contract No. DE-AC04-94AL85000 between Sandia Corporation and the United States Department of Energy. The United States Government has certain rights in this invention.